Security and privacy are becoming one of the major concerns for data elaboration, also considering the increasing globalization of the electronic supply chain. Modern computing systems must include hardware support to guarantee that valuable information is not stolen, protecting not only the user data but also the semiconductor intellectual property. While many solutions exist for these problems, they are usually applied in the last stages of the chip design, often jeopardizing the previous optimizations. Addressing hardware security during high-level synthesis (HLS) is an interesting approach to design and integrate solutions at higher levels of abstraction, co-optimizing them with the rest of the design.
In this talk, I will present recent research on HLS extensions for integrating several security features, like information flow tracking, watermarking and obfuscation. I will also present the other face of the coin: how HLS tools can be effectively compromised to become powerful attack vectors. Finally, I will outline the open challenges for addressing hardware security during high-level design.
